<?xml version="1.0" encoding="UTF-8"?>
<preferences>
 <debug showDebugMenu="0" />
 <systemtable filter="Default">
  <columns>
   <connections preferredWidth="63" />
   <irq preferredWidth="34" />
  </columns>
 </systemtable>
 <clocktable>
  <columns>
   <clockname preferredWidth="272" />
   <clocksource preferredWidth="272" />
   <frequency preferredWidth="252" />
  </columns>
 </clocktable>
 <library expandedCategories="Project,Library" />
 <window width="1100" height="800" x="227" y="100" />
 <hdlexample language="VERILOG" />
 <generation path="src/core_gen/_PROJECT_NAME_" />
</preferences>
